摘要
提出了一种基于FPGA的多通道大容量FIFO设计方案。在高速数据采集板卡中,高速大容量FIFO决定了数据采集的深度与速度。为了满足高速数据采集板卡FIFO速度高、容量大以及体积小的要求,采用SDRAM与FPGA联合设计的方案。取SDRAM价格低、存储空间大、速度快的特点,同时利用FPGA解决SDRAM接口控制逻辑复杂的问题,将存储空间封装为FIFO接口。完成了SDRAM状态控制器、FIFO地址管理器以及FIFO逻辑接口的设计与实现。在Modelsim平台上完成了基于Micron Technolog公司SDRAM模型的数据读写仿真。最后,在一块PXI板卡上完成了实物测试,分析了时钟频率、延时参数以及读写速率对误码率的影响,并给出调整方案。实现了8路16 M存储深度16bits位宽异步双口FIFO,读写速度可达128 Mbps,为高速数据采集系统提供可靠的数据存储平台。
proposed a method of Multi-channel FIFO with mass storage facility based on FPGA. In the high-speed sample board, the speed and capability of the system depend on the FIFO. In order to fulfil high-speed sample board requirements high-speed, huge facility and little volume, sleeted SDRAM and FPGA to accomplish. The SDRAM has high-speed, huge capability and low-cost but complex. Taking the advantage of FPGA to make up the complexity of SDRAM. , use the FPGA to make the logic of the FIFO, accomplished the SDRAM state controller FIFO address management and FIFO Interface logic. Then accomplish simulation on the Modelsim with a SDRAM model designed by Micron Technolog. At last, applying this method on a PXI board. Analysed the influence of clock frequency, delay parameter and read-write Frequency to Bit Error, then gived the rectify solution. Realized eight channel FIFO with 16 M storage deep, asynchronous dual-port, 16 bits wide and a speed of 128 Mbps. Providing a reliable data storage platform for the high speed data acquisition system.
出处
《电子测量技术》
2017年第8期193-197,共5页
Electronic Measurement Technology
