摘要
针对航天高速高可靠FPGA接口时序测试,分析了FPGA接口类型及测试需求,介绍了一种基于时序路径的FPGA接口时序测试方法,结合时序路径模型,阐述了异步总线接口时序测试的测试流程和计算方法,并给出实际案例。该方法集成了功能仿真和静态时序分析的优点,特别适合极限工况下的FPGA接口时序验证,已经应用到多个航天高可靠FPGA接口测试中,与传统的动态门级时序仿真相比,能显著提高验证效率和测试覆盖率。
Aiming at the high speed and reliable FPGA inte^ace timing sequence verification on space- flight, the FPGA inte^ace type and test specification is analyzed, and an FPGA interface timing verification method based on the timing sequence path is introduced, and the test flow and calculation method which is based on the timing path model and applied in the timing test of asynchronous bus interface is clarified. The advantage of function simulation with static timing analysis are integrated in this method which is suitable for the timing verification of limiting condition especially and is applied in several high reliable FPGA tes- ting on spaceflight. By comparing with the traditional timing simulation of gate-level, the verification effi- ciency and coverage can be improved by using the method introduced in this paper.
出处
《航天控制》
CSCD
北大核心
2017年第4期79-84,共6页
Aerospace Control
