摘要
二维离散小波变换是一种常用的图像处理方法.由于其计算量大,常被设计为硬件电路实现.现有二维离散小波变换的硬件架构均需要存储大量输入图像数据,存储开销较大.为此,笔者设计了一种高性能的二维离散小波变换架构,使用了一种横向扫描的串行二输入无乘法器架构,并消除了片外存储需求.对于一幅N×N的输入图像,系统的总存储需求缩减到10 N字节.另外,文中还使用了正则有符号数乘法器替代传统乘法器,将关键路径延时缩短至约一个加法器延时.经过硬件分析,对比现有其他架构,本架构的总晶体管数量减少4%,硬件效率提高了33%以上.
Two-dimensional （2-D） Discrete Wavelet Transform （DWT） is a commonly used image processing method. Due to its large amount of computation, it is often implemented in the hardware circuit to meet the need of high throughput. The existing hardware architectures have a large storage requirement for the input data. Therefore, a hardware efficient 2-D DWT architecture using the line-based and dual-scan method without multipliers is proposed. The total ram requirement of the proposed architecture is reduced to 10N bytes, while the off-chip RAM is not required. Besides, a Critical Path Delay（CPD） of one full- adder delay is achieved by using Canonic Sign Digit（CSD） multipliers. The estimated hardware requirement shows that the proposed architecture involves at least a 4% smaller number of transistors and 33% less transistor count-delay-product（TDP） than the existing architectures.
出处
《西安电子科技大学学报》
EI
CAS
CSCD
北大核心
2017年第4期138-143,共6页
Journal of Xidian University
基金
国家自然科学基金资助项目(61474080)
关键词
离散小波变换
超大规模集成电路
集成电路设计
无乘法器
无片外存储
discrete wavelet transforms
very large scale integration
integrated circuit design
multiplier-tess
off-chip random access memory less
