摘要
虽然传统的等价性验证方法如BDD或布尔SAT等能够完成低层次的电路验证,但针对抽象层次较高的电路描述验证效率较低,基于多项式的数学方法能够从字级到位级形成统一的电路描述,为高效率地完成等价性验证提供理论依据。探讨组合逻辑电路的多项式描述方法,并以多项式理想的良性基为基础,给出一种高层次等价性验证算法,并针对多种基准电路进行实验,以验证算法的性能。
The traditional equivalence verification methods such as BDD or Boole SAT can verify the circuits described at low-level,but those methods can not efficiently verify the circuits with high-level describing.The mathematic methods based on polynomial can give a uniform describing from bit-level to word-level which are the theory basement for efficient verification.This paper discusses a polynomial method of combinational logic circuit and gives a high-level equivalence verification method on the polynomial well-behaved bases,of which the experiment with some benchmark circuits can test the performance of this algorithm.
作者
范德会
FAN Dehui(College of Automobile and Traffic Engineering, Heilongjiang Institute of Technology, Harbin 150001, China)
出处
《黑龙江工程学院学报》
CAS
2017年第3期30-32,共3页
Journal of Heilongjiang Institute of Technology
基金
黑龙江工程学院博士基金项目(2012BJ08)
关键词
等价验证
多项式良性基
形式验证
组合逻辑电路
equivalence verification
polynomial well-behaved bases
formal verification
combinational logic circuit
