摘要
为了减少大素数生成时间并加快RSA(Rivest,Shamir&Adleman)公钥密码算法的加解密速度,并行化实现了小素数试除和Miller-Rabin素性测试两大关键步骤,使其在进行素性测试的同时能进行小素数试除,从而大幅减少了小素数试除单独运算消耗的时间.为了加速Miller-Rabin素性测试须要反复调用的模乘运算单元,采用一种基于字的高基Montgomery算法及多级流水结构,设计了一种可配置的高速模乘运算电路.经FPGA(现场可编程门阵列)测试,在100 MHz频率下,生成的512bit大素数的平均耗时约为75ms,生成的1 024bit密钥对的平均耗时约为166ms,耗时只有参照结果的54.2%左右.
In order to reduce operation time of big prime number generation algorithm and accelerate the speed of RSA（Rivest,Shamir Adleman）encryption and decipherment,the two key steps,sieve function and Miller-Rabin test,were parallelly achieved.So sieve function can run at the same time when Miller-Rabin test is running.It greatly reduces the sieve function operation time.To accelerate modular multiplication operation unit which is repeatedly used in Miller-Rabin test,a configurable high-speed modular multiplication operation circuit was designed.The circuit was based on highradix Montgomery algorithm and multilevel pipeline structure.Through the FPGA（field programmable gate array）verification,the generation time of 512 bit big prime number is 75 ms and the generation time of 1 024 bit RSA keys is 166 ms at the operating frequency of 100 MHz.The time is about54.2% of paper proposed.
出处
《华中科技大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2017年第6期1-4,20,共5页
Journal of Huazhong University of Science and Technology(Natural Science Edition)
基金
国家自然科学基金资助项目(61006020)
科技部科技型中小企业技术创新基金资助项目(14C26214422753)
湖北省重大科技项目(2015ACA063)
中央高校基本科研业务费专项资金资助项目(2014TS041)
