摘要
为了解决目前嵌入式液晶显示技术中存在的显示驱动支持分辨率低、数据更新慢及控制灵活性差等问题,设计了一种基于现场可编程门阵列(FPGA)的LVDS接口的液晶显示驱动。对数据缓存技术中数据读写控制等关键问题进行了分析,研究了对液晶显示驱动时序和低电压差分信号(LVDS)传输时序。基于FPGA构建缓存控制模块和显示控制模块,实现数据快速更新及LVDS接口液晶显示屏的显示。通过QuartusⅡ软件,对缓存控制模块控制时序进行了采样分析验证。验证结果表明:第二代双倍数据率同步动态随机存取存储器(DDR2 SDRAM)在166 MHz下工作,LVDS接口液晶显示屏分辨率为1 024 pixel×768 pixel,位宽为16 bit时,数据更新率达82 MHz,且控制灵活,能够满足目前对液晶显示驱动的需求。
In order to solve the problems such as low resolution,low data update rate and poor control flexibility in display driver of current embedded liquid crystal display( LCD) technology,a low-voltage differential signaling( LVDS)-interfaced LCD driver based on field-programmable gate array( FPGA) was designed. The key problem in data cache technology such as data reading and writing control method was analyzed,and the LCD driver timing together with LVDS transmission sequence was studied. The cache control module and display control module were built based on FPGA to achieve the high data update rate and the display of LVDS-interfaced LCD screen. By Quartus II software,the sampling and the control timing of the cache control module were analyzed. The experimental results show that the data update rate can reach up to 82 MHz with a flexible control mode under the condition of 166 MHz double-data-rate two synchronous dynamic random access memory( DDR2 SDRAM),the resolution of LVDS-interfaced LCD screen 1 024 pixel × 768 pixel and the bit wide 16 bit. The designed LCD driver can meet the demands well.
出处
《河南科技大学学报（自然科学版）》
CAS
北大核心
2017年第5期16-19,24,共5页
Journal of Henan University of Science And Technology:Natural Science
基金
国家自然科学基金项目(51205108)
河南省高等学校重点科研基金项目(15A535001)
