期刊文献+

一种新型交错并联同相降压升压DC/DC转换器 被引量:5

A novel Interleaved Non-Inverting Buck Boost DC / DC Converter
下载PDF
导出
摘要 为了有效降低电流纹波和提高转换器效率,提出一种新型交错并联同相降压升压DC/DC转换器。提出的结构通过采用输入/输出(I/O)磁耦合交错并联和阻尼网络技术,降低了开关的电压应力、内部电压振荡和I/O电流纹波,并提升了转换器的效率。采用状态空间平均法,在连续导通模式下分析了提出转换器的稳态运行,从理论上证明了其优势。样机的功率设置为360 W,输出电压为36 V,模拟结果以及实验结果显示,当输出电流为6 A时,转换效率最高达到96%,最大输入电流纹波百分比仅为9.4%,相较于其他类似转换器,提出的转换器具有效率较高和I/O电流纹波较低的优势。 In order to effectively reduce the current ripple and improve the efficiency of the converter, a novel interleaved non-inverting buck boost DC/DC converter is proposed. The proposed structure reduces the voltage stress of the switches ,the internal voltage oscillation and the I/O current ripple,and improves the efficiency of the converter by using the input/output(I/O) magnetic coupling interleaving and damping network technology. By using the state space averaging method, the steady state operation of the converter is analyzed in the continuous conduction mode, and its advantages are proved theoretically. Prototype of the power is set to 360 W, output voltage is 36 V, the simulation results and experimental results show that when the output current is 6 A, the maximum conversion efficiency reaches 96% ,maximum input current ripple percentage is only 9.4%. Compared to other similar converters, the proposed converter has the advantage of higher efficiency and lower I/O current ripple.
出处 《电子器件》 CAS 北大核心 2017年第1期249-255,共7页 Chinese Journal of Electron Devices
关键词 同相降压升压转换器 交错并联 低纹波电流 阻尼网络 non-inverting buck boost DC/DC converter interleaved low ripple current damping network
  • 相关文献

参考文献6

二级参考文献41

  • 1王飞,余世杰,苏建徽,沈玉梁.太阳能光伏并网发电系统的研究[J].电工技术学报,2005,20(5):72-74. 被引量:183
  • 2金科,杨孟雄,阮新波.三电平双向变换器[J].中国电机工程学报,2006,26(18):41-46. 被引量:45
  • 3童亦斌,吴峂,金新民,陈瑶.双向DC/DC变换器的拓扑研究[J].中国电机工程学报,2007,27(13):81-86. 被引量:125
  • 4应建华,陈嘉,王洁.低功耗、高电源抑制比基准电压源的设计[J].Journal of Semiconductors,2007,28(6):975-979. 被引量:6
  • 5Paul R Gray,Paul J Hurst.模拟集成电路的分析与设计[M].北京:高等教育出版社,2005:201-202. 被引量:4
  • 6CMOS模拟集成电路设计(第二版)/[美]艾伦(Allen,P.E)等著,冯军译.-北京:电子工业出版社.2005.3. 被引量:3
  • 7Chen J J. Integrated Current Sensing Circuits Suitable for Step- Down DC/DC Converters. Electron Lett ,201M ,40 (3) :200-201. 被引量:1
  • 8Corsi M. Current Sensing Schemes for Use in BiCMOS Intergrated Circuits. IEEE Proceedings of the 1996 Bipolar/BiCMOS Circuits and Technology Meeting, New York, USA, 1995:55-57. 被引量:1
  • 9Chi Yat Leung, Philip K T Mok, Ka Nang Leung, et al. An Integrated CMOS Current-Sensing Circuit for Low-Voltage Current- Mode Buck Regulator [ J ]. IEEE Transactions on Circuits and Systems II : Express Briefs,2005,52 (7) : 394 - 397. 被引量:1
  • 10Hiroki Sakurai, Yasuhiro Sugimoto. Design of a Current-Mode, MOS, DC-DC Buck Converter with a Quadratic Slope Compensation Scheme [ J ]. Chuo University, 1 - 13 - 27, Kasuga, Bunkyo-ku, Tokyo, JAPAN, IEEE ,2005 :671-674. 被引量:1

共引文献131

同被引文献31

引证文献5

二级引证文献10

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部