摘要
作为JEDEC最新的AD/DA采样数据传输协议,JESD204B协议新增了对多通道串行传输的同步支持。为了确保多通道同步传输的准确性,发送端同步电路采用Verilog HDL设计并实现了协议规定的码群同步,初始通道对齐与的同步字节替换等功能。Modelsim仿真结果验证了发送端同步电路符合协议要求,Design Complier(0.18μm工艺库)综合结果表明电路在数据传输阶段的处理频率达到255.03 MHz,可应用于JESD204B高速串行接口电路设计中。
As the latest version of AD/DA sampled data transmission standard that proposed by JEDEC ,JESD204B added the support for the synchronous serial transmission through multi-link. In order to ensure the accuracy of multi-link synchronous transmission,transmission synchronization circuit was designed by Verilog HDL and imple- mented the specified functions of the standard, which is CGS, ILAS and Sync Octet Replacement. The simulation result of Modelsim verified that the transmission circuit consistent with requirements of the protocol. The synthesis result of Design Complier（ 0.18 μm process library）showed that the circuit can reach the 255.03 MHz processing frequency during the data transmission, according to which it is able to apply in the circuit design of JESD204B high speed interface.
出处
《电子器件》
CAS
北大核心
2017年第1期118-124,共7页
Chinese Journal of Electron Devices
