摘要
为了减少复杂设计中可能的亚稳态风险,不少公司都采用工具或人工来检查设计中存在跨时钟域的问题。传统的检查方法只能检查设计中是否做了跨时钟域的处理,却无法检查处理得是否合理,而静态Formal验证技术采用数学穷举的方法,利用断言对设计中的同步器进行快速验证,确保数据的可靠传输,有效避免了一些设计缺陷。Mentor公司的Questa CDC和Formal工具可以对设计进行跨时钟域的检查,并可用Formal引擎证明设计中跨时钟域同步器与其断言的一致性,可极大地提高复杂设计的验证效率和鲁棒性。
In order to reduce the risk of metastability effects, different tools or manual checking for clock domain crossing issues are adopted by many companies. The traditional checking methods can check whether CDC issues are handled or not, but can＇ t prove whether they are handles correctly. Static verification technology with assertions can avoid the CDC bugs more effectively with mathematics exhaustive method, and make sure the data can be transferred more reliably. Mentor Graphic＇ s Questa CDC and Formal tool provides the clock domain crossing checking effectively, and verifies the consistency between CDC synchronizers and their assertion properties via Formal engine, which can improve the verification efficiency and design robustness greatly.
出处
《中国集成电路》
2017年第3期70-75,共6页
China lntegrated Circuit
