摘要
针对工业上对计数器的需求以及计数器扩展存在的问题,充分应用FPGA的并行处理功能,提出了一种模块内部串行处理,各模块间并行执行的计数器IP核的设计方法;设计了系统的电路结构,指令格式,并行处理模块电路和串行处理流程程序,研制的计数器IP核为具有多达14个16位或6个32位的计数器,能够自动重新装载计数参数,选择计数输入脉冲滤波参数等功能.经仿真验证了研制的计数器IP核功能的正确性.
To meet the demand of counters and solve the problem of their extension in industry, this design uses the parallel processing function of FPGA to propose a design of the counter IP core which features the module internal serial processing and each module parallel executing. We design the circuit configuration of the system, instruction format, parallel processing module circuit and serial processing procedures. The IP core includes 14 16-bit or 632-bit counters. When the count value of each counter overflows, the counter will reload the count parameter automatically, and choose pulse filtering parameter by programming. The simulation results show the correctness of the IP core functions.
出处
《广西科技大学学报》
2017年第2期48-54,共7页
Journal of Guangxi University of Science and Technology
基金
广西自然科学基金项目(2014GXNSFAA118392)
广西教育厅科研项目(YB2014209)资助
