摘要
针对传统的数字电视隐藏式字幕解码与显示方案中广泛采用专用解码芯片,其代码不易移植、接口不易修改、功能不易扩展以及额外的芯片花费多等问题,提出了一种采用FPGA作为处理芯片,研究设计了基于SMPTE协议和708CC标准的隐藏式字幕解码与显示方案。该方案采用Verilog HDL硬件描述语言进行编程,实现了隐藏式字幕原始数据的提取,以及DTVCC数据包、字幕服务数据的重组。并对字幕服务数据解码,实现了字幕的叠加显示。同时提出并应用了一种待显示字符的叠加方法,实现了字幕窗口、字幕字符的定位。测试结果表明,FPGA运行稳定,实现了隐藏式字幕的解码与显示。
The special decoder chip used in the traditional DTVCC （ Closed Caption, CC） display and decoding scheme suffers difficult code transplant, the interface modification, inflexible function and extra chip cost. In view of the above problems, a new scheme using FPGA is proposed based on SMPTE protocol and 708CC standard. This scheme uses the Verilog HDL hardware description language for programming, implements the extraction of the closed caption original data, realizes the reorganization of DTVCC data packets, and then reorganizes the service data and decodes caption service data. Finally, the overlay display of closed caption is realized. A superposition method is al- so proposed and used to display the characters, which can be used to realize the positioning of the caption window and the location of the caption character. The test results show that the FPGA is stable and capable of the decoding and display of the closed caption.
出处
《电子科技》
2017年第2期149-152,160,共5页
Electronic Science and Technology
