摘要
简述了一种基于CPLD的数字钟设计方案,文中所设计的数字钟是一种用数字电路技术实现时、分、秒计时的装置,与机械式时钟相比具有更高的准确性和直观性,且无机械装置,具有更长的使用寿命,因此得到了广泛的使用。通过使用EDA软件MAX+plusⅡ设计数字钟系统,阐述了自上向下和层次化设计方法及电路微型化的可行性。利用VHDL硬件描述语言结合CPLD可编程器件进行数字钟的设计,并通过数码管驱动电路动态显示计时结果,进一步说明CPLD器件值得在电路研究、设计中推广。
This paper describes a digital clock design scheme based on CPLD and the digital clock is designed in this paper a kind of when using a digital circuit technology, minutes and seconds timing device, has higher accuracy compared with the mechanical clock and intuitive, and no mechanical device, has a longer service life, therefore has been widely used. Through the use of EDA software MAX＋plusⅡ digital clock system design,this paper expounds the downward and hierarchical design method and circuit on the feasibility of miniaturization. By using VHDL hardware description language with CPLD programmable devices for the design of digital clock, and through the dynamic display of digital tube driver circuit timing results, further illustrate the CPLD device is worth popularizing in the research,design the circuit.
出处
《自动化与仪器仪表》
2017年第1期35-37,40,共4页
Automation & Instrumentation
