摘要
随着高k金属栅工程在45 nm技术节点上的成功应用,该技术已成为亚30 nm以下技术节点不可缺少的关键模块化工程。同时,如何保证高k金属栅能够在集成过程中得到有效的平坦化,保证器件正常性能也成为了金属后栅工艺的关键技术之一。本文提出的的金属栅反应离子刻蚀+介质再沉积+化学机械平坦化的技术,能够有效对金属栅极进行平坦化,且能避免金属栅极平坦化过程中较大面积区域的"金属过蚀"现象。
Here,we addressedthe ＂over-etching＂problem,originated from the conventionalplanarization of the high-k metal gate in fabricating advanced complementary metal oxide semiconductor（ CMOS） devices with nanoscale feature size（ 30 nm）. The novel planarization technique,compatible with the state-of-the-art integrated circuit fabrication technology,mainly included 3-steps： reactive ion etching,deposition of tetraethyl orthosilicate layerand chemical mechanical polishing（ CMP）. The impact of the planarization conditions on the surface and cross-sectional structures of the high-k metal gate was investigated with scanning electron microscopy for process optimization. The test results show that the newly-developed planarization method outperformed the conventional CMP,because it effectively planarized the high-k metal gate and significantly weakened the large-area corrosion / erosion of the gate＇s metal-layer. We suggest that the novel technique be of some technological interest in fabrication of highk metal gate for the CMOS devices with feature size ≤22 nm.
出处
《真空科学与技术学报》
EI
CAS
CSCD
北大核心
2016年第9期1030-1033,共4页
Chinese Journal of Vacuum Science and Technology
