摘要
10GBASE-KR变速箱的功能是实现156.25 MHz下66 bit数据与644.53 MHz下16 bit数据之间的通信。该文在深入研究万兆以太网物理编码子层(Physical Coding Sublayer,PCS)的功能以及变速箱原理的基础上,提出一种新的变速箱实现方法,将其分成读写数据转换和异步FIFO(First In First out)两个模块,完成发送通道和接收通道的设计。该方法有效减少了存储器的数目,使存储器数目由原来的528个减少到82个。本设计使用Verilog硬件描述语言,采用Model Sim进行功能仿真,并利用EDA(Electronic Design Automation)工具完成逻辑综合。仿真结果表明,该方法实现了变速箱的功能要求,并具有面积小、速度快的特点。
The function of gearbox is to achieve the communication between the 66 bit data of 156.25 MHz and 16 bit data of 644.53 MHz in10GBASE-KR.On the basis of deep research of Physical Coding Sublayer（PCS） function of the 10 Gigabit Ethernet and the theory of gearbox,a kind of gearbox design is given out,which is divided into two modules,the data conversion and asynchronous FIFO（First In First Out）,to complete design of the transition and receive channels.It can reduce the number of memory effectively,from 528 to 82.The design uses Verilog hardware description language and adopts Model Sim to implement the functional simulation.What＇s more,the logic synthesis is completed with the EDA（Electronic Design Automation） tools.The result shows it can meet the function demand of the gearbox,and it can reduce the area and improve the speed.
出处
《微型机与应用》
2016年第13期31-33,36,共4页
Microcomputer & Its Applications
