摘要
针对当前采用正则表达式匹配的深度报文检测系统匹配效率低下,难以满足高速网络线速处理的问题,本文提出了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)的深度报文检测系统。该系统采用模块化架构,充分利用FPGA并行处理的特点,通过流水线设计来提升深度报文检测系统的处理速率。
The current deep packet inspection systems using regular expression matching faces the problems that it cannot meet the wire-speed processing of high-speed network, this paper presents a field-programmable gate array-based deep packet inspection system. The system adopts a modular architecture, take full advantage of parallel processing characteristics ofFPGA. Enhance the processing speed of deep packet inspection system through pipelined design.
出处
《电子设计工程》
2016年第9期147-149,共3页
Electronic Design Engineering
基金
国家科技支撑计划项目(2014BAH30B01)
关键词
现场可编程门阵列
深度报文检测
正则表达式
流水线设计
field programmable gate array
deep packet inspection
regular expression
pipelined design
