摘要
介绍了一款可应用于DDR SDRAM控制器的基于标准单元的全数字延时锁定环(DLL)。该DLL可集成性和工艺兼容性好,可以减少DLL的设计时间和设计复杂度,非常适合系统级芯片使用。该设计采用0.18um CMOS数字工艺实现最终版图,工作频率范围达到200MHz至400MHz,无谐波锁定出错,且闭环特性可以跟踪工艺、电压、温度(PVT)变化。仿真结果表明该设计能够产生DDR SDRAM控制器规范所要求的一段固定延时(tSD)来保证DDR SDRAM控制器正确捕获存储器输出数据(DQ)。
An all-digital,cell-based Delay-Locked Loop (DLL) for DDR SDRAM controller applications is designed.The all-digital DLL can easily be ported to different processes in a short time.Thus,it can reduce the design time and design complexity of the all-digital DLL, making it very suitable for system-on-chip applications.Fabricated in 0.18um CMOS technology,frequency operating range of the all-dig-ital DLL ranges from 200MHz to 400MHz without the harmonic-locking issue and its close-loop characteristic tracks the process,voltage, temperature (PVT) variations.Simulation results show that the all-digital DLL can generate the required fixed timing delay (tSD)for DDR SDRAM controller to capture the output data (DQ) correctly.
作者
鲁顺
黄凯
LU Shun, HUANG Kai (National ASIC System Engineering Research Center,Southeast University,Nanjing 210096,China)
出处
《电脑知识与技术》
2008年第12Z期2171-2173,共3页
Computer Knowledge and Technology
