摘要
针对秒表检定规程已经更新和检定仪携带不便的问题,提出了一种基于FPGA的秒表检定仪设计方法。首先,该秒表检定仪的设计方法采用Verilog硬件描述语言,以QuartusⅡ为设计平台,采用模块化设计,利用FPGA的高时间精度,数码管驱动电路精准地动态显示计时结果,并且创新性地采用电/机转换装置为撞表机构,更精准地触发秒表,提高了检测被检秒表的准确性。其次,该秒表检定仪采用模块化设计,主要由分频模块、功能控制模块、计时模块、时间设置模块、位置设置模块、显示控制模块、舵机控制模块组成。系统采用自上而下的模块设计方法,并且本设计具有外围电路少、集成度高、可靠度强等优点。实验结果表明,该秒表检定仪测试数据时间精度高,能很好地检测秒表的计时准确性,并且携带非常方便。
Aiming at the updated verification regulation of stopwatch and inconvenient carry of verification instruments,we propose a design of stopwatch calibration instrument based on FPGA.Firstly,we use Verilog hardware description language,take Quartus II as the software platform,and employ a modular design with high time accuracy of FPGA.The accurate timing results are displayed by the driver circuit of nixie tubes.The innovative use of electrical/machine conversion device for hitting the stopwatch enables more accurate triggering and improves the detecting accuracy of the subject stopwatch.The design has a clear division,and consists of a frequency module,a control module,a timing module,a time setting module,aposition setting module,a display control module,and a servo-motor control module.The system adopts a top-down module design method,and features fewer peripheral circuits,high integration,strong reliability and other merits.Experimental results verify the high precision time.It can detect the timing accuracy of the stopwatch very well,and is very convenient to carry.
出处
《计算机工程与科学》
CSCD
北大核心
2016年第3期609-616,共8页
Computer Engineering & Science
基金
甘肃省科技支撑计划(1304GKCA024)
关键词
FPGA
秒表检定仪
模块化设计
撞表机构
电/机转换装置
FPGA
stopwatch calibration instrument
modular design
the mechanism of hitting the stopwatch
electrical/mechanical conversion device
