摘要
为了实现光纤授时设备输入/输出标准IRIG_B(DC)码,提出了一种基于FPGA的IRIG-B(DC)编解码设计方案。通过Quartus II建立工程文件,采用Verilog HDL语言设计了B(DC)码编解码电路,解决了传统设计中B码准秒时刻对齐和1PPS恢复的问题。
In order to realize a port of the standard IRIG-B（DC） code for timing device based on optical fibers, a new designing scheme of IRIG-B （DC） coding and decoding based on FPGA was proposed. The coding and decoding circuits were designed by Verilog HDL in Quartus II, and the problems of the traditional B code with seconds time alignment and 1 PPS recovery was solved.
出处
《光通信技术》
北大核心
2016年第3期29-32,共4页
Optical Communication Technology
