摘要
应用FPGA设计数字电路时,芯片的运行速度优化与资源利用优化常常是相互矛盾的。以Viterbi译码器中加比选单元(ACS)的设计为例,对采用传统方法和流水线技术方法的设计进行对比,显示采用流水线技术的设计方法在占用较小系统资源情况下可以获得更高的系统运行速度,更适用于FPGA的数字电路设计。
When using FPGA to design digital circuit, the optimization of the operation speed and resource utilization of the chip is often contradictory. In this paper, taking the design of add compare select unit（ACS） of Viterbi decoder as an example, compares the design of traditional approach with the design of pipeline technology method, the result showed that the pipelining design method can get higher system running speed with less system resource occupation, more suitable for FPGA digital circuit design.
出处
《计算机时代》
2016年第2期42-43,52,共3页
Computer Era
