摘要
介绍了逐次逼近模数转换器(SAR-ADC)的原理结构和研究现状,主要对SAR-ADC中的DAC、比较器、校准方法等主要模块进行了讨论。基于精度、速度、功耗的考虑,分别对SAR-ADC中的DAC结构进行分析比较,其多采用分段电容阵列或差分电容阵列。简述了比较器在功耗、速度、精度方面的结构调整。基于降低非理想效应,提高精度目的,对比分析了3种校准方法。为不同电路选择适当校准提供参考依据。最后总结了目前SAR-ADC的发展趋势。
The structure and status of successive approximation analog-to-digital converter （SAR ADC） was introduced in this work, as well as the discussion of main modules in the SAR-ADC, such as DAC, the comparator and calibration method. The analysis of DAC was made in consideration of speed, resolution or power.,and the main structure was split-capacitor or differential-capacitor. To reduce the non-ideal effects and improve the resolution, comparison of three calibration method was introduced later. Finally, direction and challenge relevant to SAR-ADC were introduced and summarized briefly.
出处
《电子设计工程》
2015年第15期8-12,共5页
Electronic Design Engineering
基金
贵州省重点实验室能力建设项目(黔科合计Z字[2010]4006)
贵州省科学技术基金(黔科合J字[2014]2067号)
贵州大学博士基金(贵大人基合字(2013)20号)
关键词
逐次逼近
模数转换器
DAC
比较器
校准
approximation analog-to-digital converter
DAC
comparator
calibration
