期刊文献+

A low power wide tuning range baseband filter for multistandard transceivers 被引量:1

A low power wide tuning range baseband filter for multistandard transceivers
原文传递
导出
摘要 This paper presents the design and implementation of a low power wide tuning range baseband filter with an accurate on-chip tuning circuit for reconfigurable multistandard wireless transceivers. The realized low pass filter (LPF) is a six-order Butterworth type by cascading three stage active-Gm-RC biquadratic cells. A mod- ified linearization technique is used to improve the filter linearity performance at low power consumption. A new process-independent transconductor matching circuit and a new frequency tuning circuit with frequency compen- sation are proposed to achieve a high precision filter frequency response. The proposed LPF is realized in a 130 nm standard CMOS technology. The measured results show that the LPF exhibits a high bandwidth programmability from 0.1 to 25 MHz with a tuning frequency error less than 2.68% over the wide tuning range. The power consump- tion is scalable, ranging from 0.52 to 5.25 mA, from a 1.2 V power supply while achieving a 26.3 dBm in-band IIP3. This paper presents the design and implementation of a low power wide tuning range baseband filter with an accurate on-chip tuning circuit for reconfigurable multistandard wireless transceivers. The realized low pass filter (LPF) is a six-order Butterworth type by cascading three stage active-Gm-RC biquadratic cells. A mod- ified linearization technique is used to improve the filter linearity performance at low power consumption. A new process-independent transconductor matching circuit and a new frequency tuning circuit with frequency compen- sation are proposed to achieve a high precision filter frequency response. The proposed LPF is realized in a 130 nm standard CMOS technology. The measured results show that the LPF exhibits a high bandwidth programmability from 0.1 to 25 MHz with a tuning frequency error less than 2.68% over the wide tuning range. The power consump- tion is scalable, ranging from 0.52 to 5.25 mA, from a 1.2 V power supply while achieving a 26.3 dBm in-band IIP3.
出处 《Journal of Semiconductors》 EI CAS CSCD 2015年第4期131-142,共12页 半导体学报(英文版)
基金 supported by the Scientific Research Plan Projects of Hebei Education Department(No.Q2012019)
关键词 low power baseband filter frequency tuning low power baseband filter frequency tuning
  • 相关文献

参考文献15

  • 1Kim J, Silva-Martinez J. Low-power, low-cost CMOS directconversion receiver front-end for multistandard applications. IEEE J Solid-State Circuits, 2013, 4S(9): 2090. 被引量:1
  • 2Li Z, Li M, Zhao 0, et al. TD-SCDMA/HSDPA transceiver and analog baseband chipset in O.IS-flm CMOS process. IEEE Trans Circuits Syst II: Express Briefs, 20 I 0, 57(2): 90. 被引量:1
  • 3Yoshizawa A, Tsividis Y P. A channel-select filter with agile blocker detection and adaptive power dissipation. IEEE J SolidState Circuits, 2007, 42(5): 1090. 被引量:1
  • 4Shih H Y, Kuo C N, Chen W H, et al. A 250 MHz 14 dB-NF 73 dB-gain 82 dB-DR analog baseband chain with digital-assisted DC-offset calibration for ultra-wideband. IEEE J Solid-State Circuits, 2010, 45(2): 338. 被引量:1
  • 5Tong Tao, Chi Baoyong, Wang Ziqiang, et a1. A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth. - Journal of Semiconductors, 2010, 31(5): 055010. 被引量:1
  • 6Cheng Xin, Yang Haigang, Gao Tongqiang, et a1. A CMOS Crn- C complex filter with a reconfigurable center and cutoff frequencies in low-IF WiMAX receivers. Journal of Semiconductors, 2013,34(7): 075004. 被引量:1
  • 7D'Amico S, Baschirotto A. Active-Cm-RC continuous-time biquadratic cells. Analog Integrated Circuits and Signal Processing, 2005, 45: 281. 被引量:1
  • 8Giannini V, Craninckx J, D'Amico S, et al. Flexible baseband analog circuits for software de tined radio front-ends. IEEE J Solid-State Circuits, 2007, 42(7): 1501. 被引量:1
  • 9Razavi B. RF microelectronics. Upper Saddle River: Prentice Hall, 1998. 被引量:1
  • 10Youn Y S, Chang 1 H, Koh K J, et a1. A 2 GHz 16 dBm lIP3 low noise amplifier in 0.25 flm CMOS technology. IEEE International Solid-State Circuits Conference, 2003: 452. 被引量:1

同被引文献2

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部