摘要
直接数字式频率合成器 ( DDS)是一种全数字器件 ,它不可避免地会引入杂散信号。杂散多且较难预知一直是限制 DDS应用的主要因素。文章对 DDS的杂散进行了分析 ,并采用 VerilogHDL,设计了一种减少杂散的 DDS改进结构。 Matlab分析结果表明 ,所设计的 DDS杂散波明显减少 ,信噪比提高了 36d B。
Direct digital frequency synthesizer (DDS) is a digital system, so it inevitably has spurious noise, which is the key factor limiting the application of DDS In this paper, an analysis of the spurious noise in DDS is made An improved DDS structure with reduced spurious noise is designed by using Verilog HDL language Simulation by Matlab indicates that the spurious noise in the DDS decreases evidently, and the signal to noise ratio (SNR) is increased by 36 dB
出处
《微电子学》
CAS
CSCD
北大核心
2002年第2期117-119,123,共4页
Microelectronics
