摘要
针对高速印制电路板设计中存在的差分线反射问题,设计一种参数设计完全对称与传统端接相结合的差分传输线拓扑结构。依据差分线理论,得到差分线的设计参数,量化分析了主芯片TI8168与内存芯片DDR3互连中时钟信号差分传输的端接方法和端接参数。仿真结果表明,该结构可抑制差分信号的反射和差分信号引起的共模信号的反射,提高了信号传输质量。
A differential transmission line topology of the completely symmetrical design parameters combining with the traditional termination is presented for differential line reflection problems existing in the high-speed PCB design.Based on the differential line theory,the design parameters of differential lines are received.The termination method and the termination parameters of differential clock signal transmission based on TI8168 and DDR3 chips are quantitatively analyzed.Simulation results show that the topology can effectively inhibit the reflection of the common-mode signal caused by differential signal and the differential signal,and improve the signal transmission quality.
出处
《西安邮电大学学报》
2015年第2期41-46,共6页
Journal of Xi’an University of Posts and Telecommunications
基金
国家高技术研究发展计划(863计划)资助项目(2013AA014504)
西安邮电大学2013年研究生创新基金资助项目(ZL2013-22)
关键词
差分传输线
信号完整性
反射
端接
differential transmission line
signal integrity
reflection
termination
