摘要
为了准确评估工艺参数偏差对电路延时的影响,该文提出一种考虑空间关联工艺偏差的统计静态时序分析方法。该方法采用一种考虑非高斯分布工艺参数的二阶延时模型,通过引入临时变量,将2维非线性模型降阶为1维线性模型;再通过计算到达时间的紧密度概率、均值、二阶矩、方差及敏感度系数,完成了非线性非高斯延时表达式的求和、求极大值操作。经ISCAS89电路集测试表明,与蒙特卡洛仿真(MC)相比,该方法对应延时分布的均值、标准差、5%延时点及95%延时点的平均相对误差分别为0.81%,-0.72%,2.23%及-0.05%,而运行时间仅为蒙特卡洛仿真的0.21%,证明该方法具有较高的准确度和较快的运行速度。
To evaluate effects of process variations on circuit delay accurately, this study proposes a Statistical Static Timing Analysis（SSTA） which incorporates process variations with spatial correlations. The algorithm applies a second order delay model that taking into account the non-Gaussian parameters- by inducting the notion of ‘conditional variables＇, the 2D non-linear delay model is translated into 1D linear one; and by computing the tightness probability, mean, variance, second-order moment and sensitivity coefficients of the circuit arrival time, the sum and max operations of non-linear and non-Gaussian delay expressions are implemented. For the ISCAS89 benchmark circuits, as compared to Monte Carlo（MC） simulation, the average errors of 0.81%,-0.72%, 2.23% and-0.05%, in the mean, variance, 5% and 95% quantile points of the circuit delay are obtained respectively for the proposed method. The runtime of the proposed method is about 0.21% of the value of Monte Carlo simulation. The experimental results prove that the high accuracy of the SSTA is reliable.
出处
《电子与信息学报》
EI
CSCD
北大核心
2015年第2期468-476,共9页
Journal of Electronics & Information Technology
基金
国家科技重大专项(2013ZX03006004)
国家自然科学基金(61106033)资助课题
关键词
集成电路
统计静态时序分析
空间关联
非高斯非线性
工艺偏差
延时模型
Integrated Circuit（IC）
Statistical Static Timing Analysis（SSTA）
Spatial correlations
Nongaussianity and non-linearity
Process variations
Delay model
