摘要
研究稳态视觉诱发电位需要视觉刺激器生成高频刺激信号。而传统的刺激器在产生高频图像刺激时的准确性和同步性极差,并且使用不便、刺激模式单一。鉴于此,设计了一个高频视觉刺激控制器,以FPGA为控制器并采用硬件描述语言Verilog HDL设计程序,实现图像刺激的生成。实验结果显示,设计的视觉刺激控制器具备时间精度高、准确性高和同步性好的优点,能有效地生成高频刺激信号。
In some visual evoked potential（VEPs） studies, such as steady-state VEP or VEPs with high-rate reversal patterns, the stimulator is required to be capable of manipulating the screen refresh rate precisely. The computer-based stimulator driving by software program is limited in generating high accuracy and up to screen refreshing rate level visual patterns because the time-de- lay nature of the processes under the operational system. This paper introduces a new design of stimulator scheme based on FPGA, which is able to directly control the VGA interface by the specific timing sequence signals. FPGA chip of EP4CE30 programmed by hardware description language Veritog HDL is used as controller and to generate image stimulus. The device is tested in cooperated with a high performance CRT monitor to generate up to 85 Hz reversal rate stimulation with high accuracy and synchronization.
出处
《电子技术应用》
北大核心
2015年第2期35-37,41,共4页
Application of Electronic Technique
基金
国家自然科学基金项目(61271154
61172033)
关键词
视觉诱发电位
稳态反应
高频
视觉刺激控制器
FPGA
visual evoked potential
steady state response
high-rate
visual stimulation controller
FPGA
