摘要
基于System Generator系统级建模工具在Matlab/Simulink环境下完成了UART通讯模块的建模,并生成位流文件下载到Spartan-3E开发板的FPGA芯片中,实现UART通讯数据发送和接收功能。实验结果表明,System Generator系统级建模工具不仅消除了原先系统工程师与软硬件工程师之间的隔阂,而且简化了传统的FPGA开发流程。
The paper introduces the use of System Generator of Xilinx that is system level modeling tool in the MATLAB /Simulink environment for the completion of algorithm modeling of the UART procedure , generates the corresponding code to the FPGA , and realizes the function between UART communication data sending and receiving .Experiment results show that the System Genera-tor as a system level modeling tool is not only to eliminate the gap between the original system engineers and hardware and soft -ware engineers , but also to simplify the traditional development process of the FPGA .
出处
《计算机与现代化》
2015年第1期96-101,共6页
Computer and Modernization
