摘要
KLT算法已在多个领域得到成功的应用,其中特征点的排序是用来选择好的特征点跟踪的关键。针对传统排序算法计算耗时、实时性差的缺点,提出一种可并行的多层次归并排序算法并在FPGA中实现了其并行计算,同时分析了其周期精确的计算时间。结果表明该归并排序算法可以O(N)的时间复杂度完成特征点的排序,能够满足高清分辨率的图像/视频数据中KLT特征点排序的实时性要求。
The Kanade-Lucas-Tomasi feature tracker（KLT）has received special attention due to its effectiveness on image track. The sort of feature point is the key point of joining the feature detection and feature track. This paper presents a novel FPGA-based parallel merge sort architecture for the KLT feature points, then analyzes its time period. The time complexity of the parallel merge sort architecture is O（N ） . The result shows that the FPGA-based merge sort can solve the real-time KLT feature points sort problem for HD image/video resolution.
出处
《计算机工程与应用》
CSCD
2014年第21期157-161,共5页
Computer Engineering and Applications
基金
国家自然科学基金(No.60703106
No.61170121
No.61202312)
关键词
归并排序
KLT
现场可编程门阵列(FPGA)排序
parallel merge sort
Kanade-Lucas-Tomasi（KLT）
Field Programmable Gate Array （FPGA） sort
