摘要
新一代视频编码标准(High Efficiency Video Coding,HEVC)中整数DCT编码支持大小从4×4到32×32的TU块,运算量巨大。通过优化MCM单元来减少运算量,通过硬件电路复用来减少硬件资源消耗,同时使用转置模块来加速流水线,并且能适应各种不同大小的TU块。实验代码通过Verilog HDL编写,并在Altera Arria GX EP1AGX90EF1152C FPGA上综合。结果表明,该结构等待时延最多为32个时钟周期,每个时钟周期能处理32个采样点,在184 MHz的时钟频率下,能实时处理60 f/s(帧/秒)的UHD(Ultra-High-Definition 7 680×4 320)视频信号。
The integer DCT of the next generation video coding standard HEVC suffers from huge computational complexity. It supports different TU blocks from 4 ×4 to 32 × 32. An architecture is proposed in this paper which reduces the number of computations by optimizing MCM unit and saves the resources by reusing hardware implementation. Meanwhile, transpose-module speeds up the pipeline and it can adapt to different TU sizes. The architecture is coded in Verilog HDL and synthesized targeting the EP1AGX90EF1152C device from Altera Arria GX FPGA. As the result shows, 32 samples can be handled in one cycle by the proposed architecture with a latency of 32 clocks at worst, what＇ s more, it can support real-time coding of UHD 60 f/s video sequence at 184 MHz working frequency.
出处
《电视技术》
北大核心
2014年第19期101-104,119,共5页
Video Engineering
