摘要
为充分挖掘多核DSP能力,结合TI的TMS320C6678 DSP的存储器架构,分析了各个关键节点的理论数据传输带宽,展开了对多核DSP主设备(CPU内核、EDMA控制器)并行访问存储器(共享SL2、外部DDR3)的性能研究,并采用数据拷贝测试实验进行验证,最后讨论了影响带宽的因素,对多核软件设计具有一定的指导意义。
To fully exploit the capabilities of multicore DSP, the paper analyzes the theoretical bandwidth of several key nodes,and studies the parallel performance of multiple masters（CPU cores and EDMA controllers） accessing memory（shared SL2 and external DDR3） with a knowledge of TI TMS320C6678 DSP memory architecture. It is verified by tests of data copying, and finally some factors affecting memory access performance are discussed. Some reference value is provided for designing multicore software system.
出处
《微型机与应用》
2014年第13期20-24,共5页
Microcomputer & Its Applications
