摘要
针对氧化锌压敏电阻芯片在8/20μs电流冲击初期,芯片压敏电压变化较小,老化程度无法通过静态参数判别的问题,本文设计了工频过电压耐受下的ZnO压敏电阻冲击老化试验,研究了ZnO压敏电阻芯片不同冲击老化情况,耐受工频恒定不同幅值过电压过程和耐受阶段流经芯片内部电流Iin随时间的变化关系;结合双肖特基势垒理论和ZnO压敏电阻芯片Voronoi网格微观结构模型,分析试验结论。结果表明:耐受工频恒定相同幅值过电压,ZnO压敏电阻芯片经8/20μs电流冲击后老化程度越深其流过芯片内部电流Iin的初始值越大;且lin值随时间上升速率与初始冲击老化程度呈正比;相同老化程度ZnO压敏电阻芯片耐受过电压幅值越大,耐受时间越短,Iin的初始值越大。这些可为ZnO压敏电阻冲击老化劣化初期判别提供依据。
The impact aging experiment based on the tolerance of the Zinc Oxide varistor under continuous power frequency overvoltage was designed in this paper to solve the problem that the change in the breakdown voltage of the zinc oxide varistor chip at the early stage of the 8/20μs current pulse is too small to tell the aging degree of the zinc oxide varistor chip by the static parameter. Different situations of the impact aging, the tolerance of the zinc oxide varistor under different amplitudes of overvoltage and the relationship between the internal current during the tolerance （I in） and the time were studied. Experimental results were analyzedwith the help of the Dual Schottky barrier theory and the Voronoi grid model. The results showed that the larger the aging degree of the zinc oxide varistor chip impacted by the 8/20μs current pulse was, the larger the initial value of I in was; the increased rate of lin over time was proportional to the initial impact aging degree; and when the aging situations were equal, the larger the amplitude of overvoltagewas and the shorter the tolerance time was, the larger the initial value of Iin was. . These results can be used to determine the aging and deterioration degree of the zinc oxide varistor chip.
出处
《电测与仪表》
北大核心
2014年第14期32-37,共6页
Electrical Measurement & Instrumentation
基金
国家自然科学基金(61072133)
江苏省产学研联合创新资金计划(BY2013007-02)
江苏省高校科研成果产业化推进项目(JHB2011-15)
江苏省"六大人才高峰"项目
江苏省"传感网与现代气象装备"优势学科平台资助
