摘要
本文提出了一种适合ASIC实现的可编程的数字下变频器(DDC)设计方法,该DDC嵌入于4GS/s-12bit ADC中,能够处理频率为4GHz的输入信号,并提供抽取因子分别为4、8、16、32的降采样功能.设计的DDC由一个基于CORDIC算法实现的数控振荡器(NCO)和一个全半带滤波器(HB-FIR)级联结构的抽取滤波器组组成.优化半带滤波器系数和各级数据精度,提出多种改进结构优化设计,有效减少硬件开销.基于40nm CMOS工艺,完成数字下变频器的前端设计和后端实现,并进行了流片.仿真结果显示,该设计可以在500 MHz的工作时钟频率下达到设计目标,抽取因子为4模式下,最大无衰减通带带宽可达420MHz,版图面积1550*650μm2,0.9V工作电压,功耗为180.69mW.验证了该设计方法适合于高速高精度数字信号的2n下变频.
This paper proposes a programmable digital downconverter (DDC)design method for ASIC implementation.The DDC is embedded in a 4GS/s-12bit ADC and is capable of processing input signals at a frequency of 4GHz and provides extraction factors of 4Downsampling function for 8,16,16 and 32.The designed DDC consists of a numerically controlled oscillator based on the CORDIC algorithm and a decimation filter bank implemented by a full HB-FIR filter.According to the HB-FIR filter coefficient characteristics and spectral response characteristics,a variety of improved structural optimization designs are proposed in hardware implementation, reducing the area by about 50%.Based on the 40nm CMOS process,digital front-end and back-end implementations of the digital downconverter were completed and taped out.The simulation results show that the design can achieve the design goals at a working clock frequency of 500MHz.The layout area is 1550*650um^2,and the operating voltage is 0.9V.The power consumption is 180.69mW.It is verified that the design method is suitable for 2An down conversion of high-speed and high-precision digital signals.
作者
薛金鑫
马崇鹤
周磊
吴旦昱
武锦
XUE Jin-xin;MA Chong-he;ZHOU Lei;WU Dan-yu;WU Jin(Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100049,China)
出处
《微电子学与计算机》
北大核心
2019年第1期85-89,共5页
Microelectronics & Computer
基金
"新一代宽带无线移动通信网"国家科技重大专项(2016ZX03001002)
