摘要
L S MPP是一个包含 10 2 4个处理元的细粒度并行 SIMD计算机 .为了满足低级图像处理的需要 ,以二维网格互连构成 32× 32阵列 .该文介绍 L S MPP并行处理机的系统组成、处理元结构、系统控制器、存储器组织 .并对 L S
LS MPP is a massively parallel processor. It has fine grained parallelism with up to 1024 processing elements arranged in a SIMD architecture. The processing elements are arranged in 32×32 two dimensional mesh connected array for low level image processing. The processing element array chip provides an 4×8 processing element. Each processing element has a 16 bits wide ALU,eight 16 bit local registers, a data router and a data buffer. It can perform 16 bits arithmetic operations and logical operations. The data router is used for data communication with nearest four neighbors and data broadcast communication. The data buffers is used for image transfers to and from the processing elements. The array is expanded from 32×32 to 1024×1024 according to the demands. This parallel processor is of Haverd architecture, i.e., program memory area and data memory area are independent. So the array controller includes program address generator and data address generator. The system has three stager instruction pipeline. The data transform, the data communication within processing elements, and the arithmetic and logical operation among independent execution units. So that this system has high performance for image processing. In this paper, the system architecture, the components of processing element,array controller, and memory organization of LS MPP processor are described. The performance of LS MPP is also discussed.
出处
《计算机学报》
EI
CSCD
北大核心
2002年第3期292-296,共5页
Chinese Journal of Computers
基金
教育部高等学校骨干教师资助计划项目资助
