摘要
提出了一种低功耗的绝热JK触发器电路。在绝热AERL(Approved Energy Recovery Logic)反相器电路的基础上,提出了AERL反相器级联及AERL JK触发器的实现方法。在0.5微米PTM工艺下用Spice工具对提出的电路进行了模拟仿真。结果显示与传统的CMOS JK触发器和ECRL JK触发器相比,AERL JK触发器具有更低的功耗。
A low power adiabatic JK flip-flop is designed.Based on the adiabatic AERL inverter,the AERL inverter cascade circuit and the AERL JK flip-flop are realized.The characteristics of the AERL JK flip-flop are simulated using 0.5 micrometer PTM models in Spice tools.The simulation results show that the power consumption of AERL JK flip-flop is lower than ECRL and CMOS JK flip-flops.
出处
《电子世界》
2014年第13期154-155,共2页
Electronics World
基金
保定市科技局科技公关计划(13ZG025)
