摘要
异步时序逻辑电路状态的改变必须考虑外部输入信号以及对应存储器的时钟端或控制端有无信号作用,这是分析与设计的一个难点。针对这一难点进行了详细的讨论,通过系统框图给出了分析和设计的一般步骤;总结了分析和设计中对一般问题的解决方法以及应该注意的问题。通过举例验证了该方法的正确性、通用性和快速性。
One difficult point of analyzing and designing is that the external input signal, the corresponding memory clock terminal and whether there are signal functions in control terminal has to be considered in changing the asynchronous logic circuit state. How solve this problem is discussed in detail. The general steps of analysis and design are given through system frame graphs. The solution of general problems in analysis and design, and points that should be paid attention are summarized. The validity, the versatility and speed of the method are verified by examples.
出处
《计算机时代》
2014年第5期19-22,共4页
Computer Era
基金
陕西省大学生创新创业训练计划项目(项目名称:201310720011
项目编号:1718)
关键词
异步时序逻辑电路
分析和设计
系统框图
方法
asynchronous sequential logic circuit
analysis and design
system chart
method
