摘要
分析了倍频器对芯片原子钟稳定度指标的影响,并以此提出了对倍频器的设计要求。介绍了国内外几种典型的原子钟倍频器,提出了一种基于Σ-!调制的芯片原子钟专用锁相倍频器方案,并采用分离器件对该方案进行了验证,实现了与传统铷钟物理系统的闭环锁定,铷原子频标稳定度指标达4.7E-12/s,能满足原子钟的研制需求。基于该方案开展了倍频器芯片的设计和流片,实现了3.4GHz的芯片原子钟专用芯片,与物理系统进行联调锁定后稳定度指标达5.5E-11/s,表明该芯片可满足芯片原子钟的设计要求。
By analyzing the affection on atomic clock stability, the demanding for the frequency multiplier has been offered. In comparison with several typical configurations, a novel frequency multipli-er scheme consisting of synthesizer, orthogonal mixer and DDS has been designed. Guided by the design, the first prototype fabricated with individual components has been completed; the frequency stability is 4. 7E-12/s after locking, and this design can be qualified for atomic clock. Basing on the design scheme, the special 3. 4 GHz ASIC has been fabricated, and the chip-scale atomic clock incorporated the ASIC arrived to 5. 5E-11/s, which proves that the ASIC can satisfy the design requirements of chip-scale atomic clock.
出处
《宇航计测技术》
CSCD
2014年第1期37-41,共5页
Journal of Astronautic Metrology and Measurement
关键词
+芯片原子钟
倍频器
专用芯片
＋Chip-scale atomic clock
Multiplier
Special Chip
