摘要
针对CMOS集成电路的锁定效应,论述集成电路锁定效应的产生机制和失效机理,对目前国际上各大标准化组织发布实施的锁定试验方法标准进行对比分析,详细阐述JEDEC的JESD 78号标准的技术内容,包括试验分类、试验程序、试验方法、DUT偏置条件、脉冲触发条件、失效判据和抽样要求。
For latch up effect of CMOS integrated circuits, this article discussed integrated circuits＇ latch up generation and failure mechanism, carried out a comparative analysis on the relevant latch up test method standards of the major international standardization organization, and explained JESD78 standard＇s technical content, including classification, test procedure, test method, test DUT bias conditions, pulse trigger condition, failure criterion and sampling requirements.
出处
《信息技术与标准化》
2014年第1期50-53,共4页
Information Technology & Standardization
关键词
集成电路
锁定
标准
integrated circuit
latch up
standard
