摘要
给出一种基于FPGA的8051MCU的IP核设计方案，指令集与标准8051系列处理器完全兼容。采用译码--执行两级流水结构，并通过了仿真与综合，理论速度较传统8051MCU有6-10倍的提升。针对CISC流水线设计的复杂性，提出了一种高效的实现方案，可以使执行结构近满状态运行，且简便有效地解决了传统流水线所必须面对的三种冲突。设计采用Verilog HDL语言描述，并采用ModelsimSE 6.2进行功能和时序验证，将代码下载到Xilinx公司的FPGA上进行物理验证，测试了一个LED流水灯程序，结果表明软核达到了预期的效果。
A design scheme of IP Core of 8051MCU based on FPGA is proposed,which is compatible with standard 8051MCU in instruction. Using decoding - perform two pipeline stages structure,it passed through the simulation and synthesis. The theoretical speed has 6 to 10 times increasing than traditional 8051MCU. For the complexity of CISC pipeline design,an effi-cient realization is proposed,which can make the execution structure operating nearly in full state. The three kinds of conflicts which traditional pipeline must face to is solved simply and effectively. The design is described by Verilog HDL,and verified with ModelsimSE 6.2 simulator. Finally the code is downloaded into Xilinx FPGA chip to make physical test. The results of LED light water experiment show that the core achieves the expected goal.
出处
《现代电子技术》
2014年第5期80-82,共3页
Modern Electronics Technique
基金
国家自然科学基金项目(51072162)
陕西省国际合作项目(2012KW-10)
关键词
8051微处理器
流水线
控制冒险
FPGA
5018MCU
Verilog HDL
pipeline
FPGA
control hazards
