摘要
介绍一种设计基于AMBA总线的CAN控制器IP核的方法,使用VHDL硬件描述语言实现挂接在AMBA APB总线上的CAN控制器的设计;设计的控制器IP核支持CAN2.0协议,实现了CAN2.0的数据链路层协议以及部分物理层协议,设计的控制器能发送CAN2.0协议中的各种帧,具有完善的检错、纠错的能力,并且提供仅听模式和复位模式的工作方式,总线时序参数可配置。同时搭建了CAN总线系统测试平台,用设计IP核作为CAN节点的控制器完成测试验证,测试结果表明IP核成功实现了CAN控制器的功能。
Introduce a design of CAN controller IP core based on AMBA bus. The controller IP core was implemented in VHDL and then the whole design was targeted to a FPGA device. CAN controller 1P core support CAN2.0 protocoi, implement ogicai ink iayer and partia physical layer. This controller can send all frame ordered in CAN2.0 bus specification, It gets the capability of error check and error correct, listen only mode and reset mode are accepted. The CAN bus timing parameter of the IP core is configurable. And CAN bus system hardware platform have been set up for testing this controller. Result of test indicate that IP core complete function of CAN controller.
出处
《计算机测量与控制》
北大核心
2013年第10期2780-2782,2831,共4页
Computer Measurement &Control
