摘要
在通信领域,差错控制技术能有效地改善通信系统的传输性能。作者在本文中探讨了BCH码的译码算法，并用Altera FPGA 实现了BCH(31,21)码的两种硬件译码。一种是串行译码；另一种是并行译码。取得了令人满意的结果。
In the area of communication, the error-control technique can improve the performance of communication effectively. For this reason, BCH decoding algorithm is discussed and two kinds of decoders of BCH(31,21) code with Altera FPGA are presented. One is generated by serial method; the other is by parallel method. High performance is achieved.
出处
《电路与系统学报》
CSCD
2000年第4期98-100,共3页
Journal of Circuits and Systems
