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一种宽带信号产生的DDS PLL Hybrid新型结构及实现 被引量:4

A novel DDS-PLL hybrid structure for wideband signal generation
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摘要 DDS+PLL Hybrid结构兼顾DDS和PLL的优势,但也兼具DDS和PLL的缺点:宽带信号性能较差;零相位误差跟踪的实现难度大;环路稳定性差;较长的捕获时间;调频斜率受限等。提出了在传统的DDS+PLL Hybrid结构中增加频率扫描电路的方法,能够有效降低环路设计难度,提高了捕获速度。扫频电路使大带宽、短脉冲的调频信号的产生成为可能。同时提出了预失真相位补偿的方法,极大地提升了信号的脉压性能。设计了实验电路,对所提出的电路结构和相位补偿方法进行了验证。试验结果表明,在环路带宽为1MHz和2MHz时,环路的捕获时间分别减小为2.175μs和1.032μs;相位误差小于4°;信号的脉压性能接近理想,主瓣宽度与理想值相同,PLSR优于-38dB,ISLR优于-9.5dB。 The signal generator with DDS-PLL Hybrid structure possesses the advantages of wide bandwidth and high frequency resolution. There are also some drawbacks, such as the serious spurious and harmonics, the increasing of difficulties in design and realization due to the zero phase error tracking of the linearity frequency modulation (LFM) signal, the long acquisition time, and the limitation to frequency modulation (FM) rate. A novel structure by adding sweeping voltage circuitry to the classical DDS-PLL hybrid in order to overcome the shortcomings is proposed. The predistortion was also involved in the study to compensate the static phase error which improves the pulse compression qualities. A test circuitry was designed. The measurements indicate that the acquisition time is reduced to 2. 175μs and 1. 032μs corresponding to loop bandwidths of 1MHz and 2MHz separately, the total phase error is depressed to be less than 4°, and the pulse compression result is nearly ideal where the main lobe width remains as ideal, PLSR is better than -38dB, the ISLR is better than -9.5dB.
出处 《国防科技大学学报》 EI CAS CSCD 北大核心 2013年第4期103-108,共6页 Journal of National University of Defense Technology
关键词 DDS-PLL混合结构 宽带 线性扫频 预失真补偿 DDS-PLL Hybrid frequency sweeping predistortion
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  • 1Woo J C, Lim B G, Kim Y S. Modification of the recursive sidelobc minimization technique for the range-doppler algorithm of SAR imaging [ J ]. Journal of Electromagnetic Wave and Applications, 2011, 25 ( 13 ) : 1783 - 1794. 被引量:1
  • 2Pichler M, Stelzer A, Gulden P, et al. Phase-error measurement and compensation in PLL frequency synthesizers for FMCW sensors-Ⅱ: Theory[J]. IEEE Trans on Circuits and Systems I: Regular Papers, 2007, 54(6) : 1224 - 1235. 被引量:1
  • 3Kroupa V F, Cizek V, Stursa J, et al. Spurious signals in direct digital frequency synthesizers due to the phase truncation [ J]. IEEE Trans on Ultrasonics Ferroelectrics and Frequency Control, 2000, 47(5) : 1166 - 1172. 被引量:1
  • 4Zhao Z Y, Chang W G, Li X Y, et al. Design and realization of wideband radar signal simulator [ C ]. 6th International Conference on Radar, RADAR 2011, October 24 - 27, 2011, Chengdu, China. 被引量:1
  • 5Zhao Z Y, Chang W G, Li X Y, et al. Pre-distortion for DDWS system[ C]. 13th International Radar Symposium, IRS -2012, May 23 - 25, 2012, Warsaw, Poland. 被引量:1
  • 6Kao S Y, Liu S I. A digitally-calibrated phase-locked loop with supply sensitivity suppression [ J ]. IEEE Trans on Very Large Scale Integration System, 2011, 19(4) : 592 -602. 被引量:1
  • 7Chiu W H, Huang Y H, Li T H. A dynamic phase error compensation technique for fast-locking phase-locked loops [ J]. IEEE Journal of Solid-State Circuit, 2010, 45 (6) : 1137 - 1149. 被引量:1
  • 8Wu Y D, Lai C M, Lee C C, et al. A quantization error minimization method using DDS-DAC for wideband fractional-N frequency synthesizer[ J]. IEEE Journal of Solid-State Circuit, 2010, 45(11) : 2283 -2291. 被引量:1
  • 9Mitomo T, Ono N, Hoshino H, et al. A 77 GHz 90 nm CMOS transceiver for FMCW radar applications [ J ]. IEEE Journal of Solid-State Circuit, 2010,45(4): 928-937. 被引量:1
  • 10Herzel F, Osmany S A, Scheytt J C. Analytical phase-noise modeling and charge pump optimization for fractional-N PLLs [J], IEEE Trans on Circuits and Systems I: Regular Papers, 2010,57(8) : 1914 - 1924. 被引量:1

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