摘要
文章提出了一种二阶全数字锁相环的实现方法，由于采用鉴频、鉴相并置方法，同时把数字滤波器融入其中，采用小数分频器构成数控振荡器，从 TU－ 12中恢复 E1时钟信号。经硬件实验证实，电路的性能指标完全可以满足 ITU－ T的有关标准。采用全数字锁相环对系统集成有明显的好处。
In this paper,a second－ order all digital Phase－ Locked Loop is proposed,parallel connection method are used between the phase difference and the frequency difference,and the filter are permeated in,and we use the digital divider,with ratio of decimal fraction,as a digital control oscillations,then the PLL could be used to recover the E1 clock that is demapped from TU－ 12 signal.It is proved by hardware experiment that the performance can meet the ITU－ T recommendation.All digital circuits are useful in VLSI design.
出处
《微电子学与计算机》
CSCD
北大核心
2000年第5期55-58,共4页
Microelectronics & Computer
关键词
同步数字系列
抖动
锁相环
通信网
Synchronous digital hierarchy jitter phase,Locked loop,FPGA
