摘要
提出了一种能够改善高精度辐照加固设计流水线型模数转换器(ADC)动态性能指标的减式抖动电路技术.其中,基于深度伪随机数生成器所产生的伪随机数来驱动高精度数模转换器而生成所需的抖动信号,将抖动信号与ADC的输入信号相加输送给ADC进行量化,并将抖动信号从ADC量化输出中减去,以降低ADC的信噪比.结果表明,所提出的抖动电路技术能够改善ADC的静态和动态性能,特别是在ADC量化小的输入信号时.
A subtractive dither technology to improve performance for a high-resolution radiation hardening by design pipeline analog-to-digital converter was proposed. The dither signal generation is based on a deep multi-bits pseudo-random number generator driving a 5-bit high-resolution digital to analogue conversion （DAC）. This dither signal is added with analog to digital converter （ADC） input signal, sampled, quan- tized and then digitally subtracted from the ADC output, thereby causing no significant degradation signal noise ratio （SNR）. The measured results show that the proposed dither technology can efficiently improve static and dynamic performance of the ADC, especially when the ADC quantizes a small-signal input.
出处
《上海交通大学学报》
EI
CAS
CSCD
北大核心
2013年第1期129-132,137,共5页
Journal of Shanghai Jiaotong University
基金
国家自然科学基金(60906009
61176030
61076025
60970036)
模拟集成电路实验室基金(9140C0901110903)
核高基重大专项(2009ZX01028-002-002)
信息保障技术重点实验室基金(KJ-11-04)资助
关键词
抖动
流水线
抗辐照加固设计
模数转换器
dither
pipeline
radiation hardening by design
analog to digital converter （ADC）
