摘要
介绍了FPGA动态可重构技术的原理，提出一种采用常规SRAM编程FPGA来实现的动态可重构数字逻辑系统设计的新构想，并以小型时序信号发生器为例讨论了这种系统区别于传统数字逻辑系统的设计特点和应用前景。
This paper presents a new idea of designing of FPGA dynamically re-configurable digital logic system by using normal FPGA based on SRAM programming. Taking a sequence signal generator as an example, we discuss the difference between the design methods of traditional digital logic system and the dynamically re-configurable digital logic system, also the application prospect.
出处
《半导体技术》
CAS
CSCD
北大核心
2000年第4期18-21,共4页
Semiconductor Technology
基金
国家自然科学基金!69976020
