摘要
VHDL非常适用于可编程逻辑器件的应用设计。尤其在大容量CPLD和FPGA的应用设计中 ,若采用以往的布尔方程或门级描述方式 ,很难快速有效地完成。VHDL能提供高级语言结构 ,方便地描述大型电路 ,快速地完成设计。它支持设计单元库的创建 ,以存储设计中重复使用的元件。它是一种标准语言 ,它的设计描述可被不同的工具所支持 ,可用不同器件来实现。文中以数字密码锁的设计为实例 ,从方案的确定 ,各阶层的划分 ,VHDL的应用 ,介绍了VHDL自顶向下的设计方法。
VHDL is very suitable to the design of programmable logic devices. It is difficult to design large capacity CPLD and FPGA with the description method of Boolean equations or of gates. VHDL can provide high level language structure, describe large scale circuit conveniently and complete design rapidly. It supports the creation of library of components to store the components that are used repeatedly. It is a standard language. Its design description can be supported by different tools and implemented by different devices. This paper introduces the VHDL top down design method including scheme determination, hierarchy division, and VHDL application taking a digital code lock design for example.
出处
《北京化工大学学报（自然科学版）》
EI
CAS
CSCD
2000年第2期97-99,共3页
Journal of Beijing University of Chemical Technology(Natural Science Edition)
