期刊文献+

基于类定向测试的多制式视频后处理芯片验证 被引量:2

Verification for Multi-standard Video Post Processing Chip Based on Resembling Directed Test
下载PDF
导出
摘要 为加快多制式视频后处理芯片的验证进度,以约束随机化和功能覆盖率收敛技术为指导,提出基于类定向测试的芯片验证方法,给出定向测试中的权重修正过程。仿真实验结果表明,该方法能够提高覆盖盲点被击中的概率、减少重复配置,使输入输出制式覆盖率快速收敛,验证效率比传统方法提升60%~70%。 In order to cover all the combinations of input and output standard quickly and speed up the verification progress of multi-standard video post processing chip, a verification method of chips based on resembling directed test is proposed by using Constrained Random test(CRT) and Coverage Convergence Technology(CCT) as the guidance, then the essay specifies the process of weight correction in resembling directed test. The simulation data and experimental results show that this approach can improve the rate of hitting the blind spots of coverage, and reduce the repetition of configuration. Accordingly, the coverage of the combinations of input and output standard converges fast, and the efficiency of verification increases by 60% to 70% compared with traditional method.
出处 《计算机工程》 CAS CSCD 2012年第15期251-253,257,共4页 Computer Engineering
基金 国家自然科学基金资助重点项目(61036004) 国家自然科学基金资助项目(61076024)
关键词 验证进度 约束随机化 覆盖率收敛技术 类定向测试 权重修正 覆盖盲点 verification progress constrained randomization Coverage Convergence Technology(CCT) resembling directed test weight correction blind spots of coverage
  • 相关文献

参考文献10

  • 1Sagahyroon A, Lakkaraju G, Karunaratne M. A Functional Verification Environment[C]//Proc. of the 48th Midwest Sympo- sium on Circuits and Systems. Cincinnati, USA: [s. n.], 2005. 被引量:1
  • 2Su Linlin, Zhang Xiaolin. A Real-time Interactive Verification System for ASIC Design[C]//Proc. of WASE International Conference on Information Engineering. Taiyuan, China: [s. n.], 2009. 被引量:1
  • 3罗莉,夏军,邓宇.通用SPI Flash控制器的设计与验证[J].计算机工程,2011,37(8):22-24. 被引量:11
  • 4Yang Shengqi, Lu Tiehan. A Practical Design Flow of Noise Reduction Algorithm for Video Post Processing[J]. IEEE Transactions on Consumer Electronics, 2007, 53(3): 995-1002. 被引量:1
  • 5Virk K, Li Huiying, Forchhammer H. Reduced Complexity MPEG2 Video Post-processing for HD Display[C]//Proc. of 2008 IEEE International Conference on Multimedia and Expo.Hannover, Germany: [s. n.], 2008: 769-772. 被引量:1
  • 6Video Electronics Standards Association. VESA Monitor Timing Standard Ver1.0, Rev.1.0[S]. 2004. 被引量:1
  • 7Bergeron J. Writing Testbenches Using System Verilog[M]. New York, USA: Springer, 2006. 被引量:1
  • 8沈海华,卫文丽,陈云霁.覆盖率驱动的随机测试生成技术综述[J].计算机辅助设计与图形学学报,2009,21(4):419-431. 被引量:21
  • 9李渊清,张之圣.基于VMM的图像处理子系统验证平台的研究与设计[D].天津:天津大学,2010. 被引量:1
  • 10Huang Siyuan, Shao Zhiyiong. Improve Verification Productivity with Synopsys Coverage Convergence Technology[EB/OL]. [2010- 07-16]. http://www.synopsys.com.cn/information//2OO9/improve- erification-productivity-with-synopsys-coverage-convergence- technology. 被引量:1

二级参考文献46

共引文献30

同被引文献8

引证文献2

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部