摘要
比较器是Bang-Bang控制模式开关电源的核心模块。由于Bang-Bang控制模式开关电源的开关频率很高,因此对比较器的速度要求很高。通过对输入信号进行预放大,采用轨对轨的结构,实现了对比较器时延的优化。基于0.18μm工艺,利用Cadence软件,对比较器电路进行仿真验证及版图设计,上升和下降时延都小于2ns,性能较好。
Comparator is the core of switching power supply module using Bang-Bang control mode. The high frequency of switching power supply with Bang-Bang control mode demands that the comparator should have very high speed. By pre-amplifying input signal, time delay of the eomparator was optimized using rail-to-rail structure. Based on 0. 18 μm process, circuit layout was designed, and simulation was made using Cadence software. Simulation results showed that the circuit had a time delay less than 2 ns for both rising and falling edges.
出处
《微电子学》
CAS
CSCD
北大核心
2012年第4期523-526,共4页
Microelectronics
