摘要
随着SoC芯片设计复杂度的日益增加,芯片内部时钟设计也越来越复杂。基于华大九天SoC时钟设计工具ClockExplorer对SoC芯片内部模块进行了时钟树插入技术的系统研究,使用ClockExplorer工具进行时钟树综合,并进行门控时钟的插入和时钟拓扑结构的优化,从而验证国产EDA工具的功能。
As the increasing complexity of the SoC designs, the clock nets design inside the chip became more and more difficult. Systematic research about clock insert technology inside the SoC chip has been done based on ClockExplorer, a clock design EDA tool from Empyrean. This paper use ClockExplorer for the insertion of clock gating and clock topology optimization, which verifies the domestic functions of EDA tools
出处
《中国集成电路》
2012年第8期52-55,共4页
China lntegrated Circuit
基金
国家科技重大专项--EDA工具应用示范平台建设(项目编号:2009ZX01035-001-007-2)项目支持
