期刊文献+

A high-speed mixed-signal down-scaling circuit for DAB tuners

A high-speed mixed-signal down-scaling circuit for DAB tuners
原文传递
导出
摘要 A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized. Some new circuit techniques are adopted to improve its performance. A dual-modulus prescaler (DMP) with low phase noise is realized with a kind of improved source-coupled logic (SCL) D-flip-flop (DFF) in the synchronous divider and a kind of improved complementary metal oxide semiconductor master-slave (CMOS MS)-DFF in the asynchronous divider. A new more accurate wire-load model is used to realize the pulse-swallow counter (PS counter). Fabricated in a 0.18-#m CMOS process, the total chip size is 0.6× 0.2 mm2. The DMP in the proposed down-scaling circuit exhibits a low phase noise of-118.2 dBc/Hz at 10 kHz off the carrier frequency. At a supply voltage of 1.8 V, the power consumption of the down-scaling circuit's core part is only 2.7 mW. A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized. Some new circuit techniques are adopted to improve its performance. A dual-modulus prescaler (DMP) with low phase noise is realized with a kind of improved source-coupled logic (SCL) D-flip-flop (DFF) in the synchronous divider and a kind of improved complementary metal oxide semiconductor master-slave (CMOS MS)-DFF in the asynchronous divider. A new more accurate wire-load model is used to realize the pulse-swallow counter (PS counter). Fabricated in a 0.18-#m CMOS process, the total chip size is 0.6× 0.2 mm2. The DMP in the proposed down-scaling circuit exhibits a low phase noise of-118.2 dBc/Hz at 10 kHz off the carrier frequency. At a supply voltage of 1.8 V, the power consumption of the down-scaling circuit's core part is only 2.7 mW.
出处 《Journal of Semiconductors》 EI CAS CSCD 2012年第7期108-112,共5页 半导体学报(英文版)
基金 supported by the National Natural Science Foundation of China(No.61106024) the Specialized Research Fund for the Doctoral Program of Higher Education,China(No.20090092120012) the Science and Technology Program of Southeast University(No. KJ2010402)
关键词 PLL DMP down-scaling circuit CMOS PLL DMP down-scaling circuit CMOS
  • 相关文献

参考文献9

  • 1ETSI EN 300 40l V1.3.1. Digital audio broadcasting (DAB) to mobile, portable and fixed receivers. European Broadcasting Union and Union Europdenne de Radio-T616vision, 2000-04. 被引量:1
  • 2Yazdi A, Green M M. Fully integrated 533 MHz programmable switched current PLL in 0.012 mm2. Electron Lett, 2008, 44(22): 1297. 被引量:1
  • 3Yang C Y, Dehng G K, Hsu J M, et al. New dynamic flip-flops tbr high-speed dual-modulus prescaler. IEEE J Solid-State Circuits, 1998, 33(10): 1568. 被引量:1
  • 4Rabaey J M, Chandrakasn A, Nikolic B. Digital integrated cir- cuits: a design perspective. 2nd ed. Prentice-Hall lnc, 2004. 被引量:1
  • 5Soares J, Navarro J, Noije V, et al. 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS cir- cuit technique (E-TSPC). IEEE J Solid-State Circuits, 1999, 34(1): 97. 被引量:1
  • 6Zhang M, Islam S K, Haider M R. Efficient driving-capability programmable frequency divider with a wide division ratio range. IET Circuits, Devices & Systems, 2007, 1(6): 485. 被引量:1
  • 7Barale F, Sen P, Sarkar S, et al. Programmable frequency-divider for millimeter-wave PLL frequency synthesizers. 38th European Microwave Conference EuMC, 2008:460. 被引量:1
  • 8Xu Y, Wang Z G, Li Z Q, et al. Key technologies of frequency- hopping frequency synthesizer for Bluetooth RF front-end. Jour- nal of Southeast University (English Edition), 2005, 21(3): 260. 被引量:1
  • 9Tang L, Wang Z G, Xue H, et al. A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits. Journal of Semiconductors, 2010, 31(5): 055008. 被引量:1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部