摘要
实现了一种14位40MS/s CMOS流水线A/D转换器(ADC)。在1.8V电源电压下,该ADC功耗仅为100mW。基于无采样/保持放大器前端电路和双转换MDAC技术,实现了低功耗设计,其中,无采样/保持放大器前端电路能降低约50%的功耗,双转换MDAC能降低约10%的功耗。该ADC采用0.18μm CMOS工艺制作,芯片尺寸为2.5mm×1.1mm。在40MS/s采样速率、10MHz模拟输入信号下进行测试,电源电压为1.8V,DNL在±0.8LSB以内,INL在±3.5LSB以内,SNR为73.5dB,SINAD为73.3dB,SFDR为89.5dBc,ENOB为11.9位,THD为-90.9dBc。该ADC能够有效降低SOC系统、无线通信系统及数字化雷达的功耗。
A 14-bit, 40 MS/s CMOS pipelined A/D converter was designed. Operating at 1.8 V supply voltage, the A/D converter dissipated only 100 mW of power. The low power design was achieved by using NADAC and DMDAC technologies, which reduced power consumption by about 500/oo and approximately 10%, respectively. Fabricated in 0. 18 μm CMOS process technology, the A/D converter occupied a chip area of 2.5 mm×1.1 mm. For an input analog signal of 10 MHz and at a sampling rate of 40 MS/s, the A/D converter achieved a DNL of ±0. 8 LSB, an INL of±3.5 LSB, an SNR of 73. 5 dB, an SINAD of 73.3 dB, an SFDR of 89.5 dBc, an ENOB of 11.91 bits, and a THD of -90. 9 dBc. The A/D converter can effectively reduce power dissipation of SOC, wireless communication and digitized radar systems.
出处
《微电子学》
CAS
CSCD
北大核心
2012年第3期301-305,共5页
Microelectronics
