FPGA Resources Reduction by a Multiplexing Technique Applied on ANN-Based Harmonics Extraction Algorithms
FPGA Resources Reduction by a Multiplexing Technique Applied on ANN-Based Harmonics Extraction Algorithms
摘要
In this paper, a multiplexing technique is applied on a neural harmonics extraction method, based on an efficient formulation of the instantaneous reactive power theory. This approach can be used in nonlinear loads compensation with APFs （Active Power Filters）. The architecture for reference current generation, synchronized by a neural phase lock-loop, is composed of three Adaline neural networks. This leads to an important consumption of field programmable gate array resources during implementation. The proposed technique uses only one Adaline and keeps the immunity of the approach under non-sinusoidal and unbalanced conditions of voltage. Simulation results of the neural harmonics detection system connected to a reference current controller show balanced and sinusoidal source currents under various conditions. Results with experimental measurement made on an APF test bench demonstrate its good performances on harmonics filtering. Moreover, the simplified structure from the new approach called mp-q method shows a significant resource reduction.
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